1. Field of the Invention
The present invention relates to an image display apparatus provided with image forming devices arranged in a matrix. For example, the present invention is applied to a television receiver or a display apparatus for receiving television signals or display signals from a computer or the like to display images using a display panel that is provided with a plurality of surface conduction devices arranged in a matrix and a fluorescent screen receiving electron irradiation and emitting light. In particular, the present invention relates to image data adjustment means for correcting a drop in drive voltage due to electric resistance of the matrix wiring or the like on the display panel, and digital image data processing means having amplitude adjustment means for controlling the amplitude of the adjusted image data.
2. Related Background Art
Conventionally, as image display apparatuses of this type, Japanese Patent Application Laid-Open No. 8-248920 discloses an image display apparatus for calculating adjusted data using statistical operations and synthesizing an electron beam requiring value and a correction value to correct a reduction in luminance resulting from voltage drop due to wiring resistance such as resistance of electric connections to electron-emitting devices.
FIG. 63 is a block diagram of a schematic configuration of an image display apparatus according to the prior art.
The following will describe a configuration related to adjustment of image data.
First, luminance data corresponding to one line of digital image signals are added up at an adder 206, and correction factor data corresponding to the added value is read from a memory 207.
On the other hand, the digital image signals are serial-parallel converted at a shift register 204, held in a latch circuit 205 for a predetermined period of time, and inputted at predetermined timing into multipliers 208 provided for respective column wirings.
The multipliers 208 multiply the luminance data and the correction data read from the memory 207 together on a wiring basis, and transfers the data after adjusted to a modulation signal generator 20ninthe modulation signal generator 209 generates modulated signals corresponding to the data adjusted so that an image will be displayed on the display panel based on the modulated signals.
In this configuration, statistical operations are performed to determine the sum or average of digital image signals such as the addition processing performed by the adder 206 on the luminance data corresponding to one line of digital image signals so that the data will be adjusted based on the resultant value.
On the other hand, as typical signal processing means, Japanese Patent Application Laid-Open No. 01-091515 discloses a pulse width modulator having an overflow detection unit and a limiter, and Japanese Patent Application Laid-Open No. 07-273650 discloses an A/D conversion circuit having an overflow detection part and a gain limitation part.
The above-mentioned configurations, however, require large-scale hardware such as multipliers provided for respective column wirings, a memory for outputting adjusted data, an adder for supplying an address signal to the memory, and so on.
Further, the adjustment of image data may cause overflow, and hence disturbance in the display image.
The present invention has been made to solve the above conventional problems, and it is an object thereof to provide an image display apparatus that suitably compensates for the influence of voltage drop due to resistance of the matrix wiring on the display panel and internal resistance of scan means with a reduced hardware configuration so that an image will be displayed with excellent image quality.